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                               DAC FIFO mode example program
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Copyright(C) Redpine Signals 2016
All rights reserved by Redpine Signals.

This program should be used on your own responsibility.
Redpine Signals assumes no responsibility for any losses
incurred by customers or third parties arising from the use of this file. 

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Function description:
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This example explain the DAC functionality in FIFO mode.
here input samples to DAC fed using external UDMA with ping pong mode and DAC output generate on ULP_GPIO4.
Following configuration used in example.
1. DAC operation mode    : FIFO mode
2. DAC FIFO threshold    : 3
3. DAC output GPIO       : ULP_GPIO4
4. DAC input samples     : Standard sine wave samples are feed to DAC input register. 
5. Reference LDO voltage : 2.8V(Max output voltage of DAC is 2.8V)
6. M4 core clock         : 180Mhz
7. ULP Pro clock         : 90Mhz
After getting ping or pong interrupt M4 will reconfigure respective descriptor.
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Environment
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Test Board:
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Smark EVK 

Assistance software:
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None

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Usage Procedure:
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compile and run the application.

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Pass criteria:
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Observe the output on ULP_GPIO_4 pin using Logic analyzer or oscilloscope. 
The output should be sine wave with voltage up to 2.8V  then DAC output is proper and test case is pass. 
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