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                ADC single channel data acquisition.
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Copyright(C) Redpine Signals 2016
All rights reserved by Redpine Signals.

This program should be used on your own responsibility.
Redpine Signals assumes no responsibility for any losses
incurred by customers or third parties arising from the use of this file. 

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Function description:
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In this example single ADC channel will collect configured number of samples.Here following 
configuration are used in application:
1.Sampling rate : 100Ksps.
2.Input type    : Single ended.
3.Positive input to ADC : ULP_GPIO4
4.Negative input to ADC : ULP_GPIO5,For single ended data acquisition this parameter not used.
5.Reference Voltage     : 2.8V (On LDO)(To change reference voltage modify 'vref_value' variable #line36)
6.Number of sample collection for each interrupt : 1023
7.ADC output memory  : Ping memory : 0x24060800
                       Pong memory : 0x24060800 + (Number of sample collection for each interrupt * 2)
					  
In this example ADC output can be process in FIR low pass filter so enable 'FIR_FILTER_ENABLE'(#line 34)
to process ADC output in FIR filter.

FIR Filter Specification :
1.'FILTER_COEFF_23_Q15' : 
If this macro enable then 23 filter coeff used for FIR filter operation,Following configuration 
used in this filter,
a.Fs(Sampling rate)          : 5Mhz
b.Pass band ripple           : 1dB
c.Stop band attenuation      : 20dB
d.Fc(cut off frequency)      : 100Khz
e.Fstop(stop band frequency) : 300Khz
Enable '#define FILTER_COEFF_23_Q15  1'(#line 55) for above filter.

1.'FILTER_COEFF_88_Q15' : 
If this macro enable then 88 filter coeff used for FIR filter operation,Following configuration 
used in this filter,
a.Fs(Sampling rate)          : 5Mhz
b.Pass band ripple           : 1dB
c.Stop band attenuation      : 20dB
d.Fc(cut off frequency)      : 25Khz
e.Fstop(stop band frequency) : 75Khz
Enable '#define FILTER_COEFF_88_Q15  1'(#line 56) for above filter.
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Environment
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Test Board:
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Smart EVK Rev1.2

Assistance software:
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None
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MACRO usage
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1.'GAIN_OFFSET_CAL_EN'(#line39 in rsi_adc.h) 
Enable the gain and offset calculation on ADC samples,Enable this macro for printing
input equivalent voltage.here GAIN_OFFSET_CAL_EN already define
in (Options for Target --> C/C++ -->Define) 

3.'FIR_FILTER_ENABLE'(#line34 in adc_single_chnl_example.c) 
Enable this macro as one to apply the low pass filter on ADC output.

4.'CORE_CLOCK_180MHZ'(#line28 in adc_single_chnl_example.c)
Enable this macro as one to switch M4 clock to 180Mhz.

5.'FINDOUT_INPUT_VOLTAGE'(#line35 in adc_single_chnl_example.c)
Enable this macro as one for findout input to ADC based on ADC output samples.
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Usage Procedure:
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Give the input to ULP_GPIO_4 for single ended mode.
Give the positive input on ULP_GPIO_4 and negative input on ULP_GPIO_5 in differential mode.  
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Pass criteria:
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After enable 'FINDOUT_INPUT_VOLTAGE' M4 will store the equivalent input voltage from ADC output
samples in 'adc_input_eqv_vltg' buffer.

Filter enable outputs for sine tone input
1.If FILTER_COEFF_23_Q15 = 1
  In this filter max input tone can apply = Achieved sampling/50 (Cutoff freq is 100khz)
  E.g In this example sampling rate is 100ksps so max sine ton can apply 2Khz.
  Expected Result : 
  FIR input samples SNR : 59.02dB   
  FIR output samples SNR : 67.21dB

2.If FILTER_COEFF_88_Q15 = 1
  In this filter max input tone can apply = Achieved sampling/200 (Cutoff freq is 25khz) 
  E.g In this example sampling rate is 100ksps so max sine ton can apply 0.5Khz. 
  Expected Result : 
  FIR input samples SNR : 59.48dB   
  FIR output samples SNR : 73.47dB
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Note 
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1.Make sure 'DONOT_READ_DATA_FROM_MEM'(#line37 in rsi_adc.h) is not enabled.
2.Make sure 'MULTICHANNEL_ENABLE'(#line41 in rsi_adc.h) is not enabled
4.Enable  '#define  GAIN_OFFSET_CAL_EN'(#line39 in rsi_adc.h) For dc precision application
  or else disable '#define  GAIN_OFFSET_CAL_EN' macro. 
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